
Block Diagram
VREF (10)
8
Rt/Ct
(5)
4
OSC
VREF
12µA
Latch/SS
(4)
3
2.5V
1.5V
OVP
1V
GND
(6)
5
Startup
Circuit
VSTR (1)
1
Enable
5V Ref
SQ
R
SQ
R
Reset
Circuit
Startup
Circuit
OVP
7 VCC
(8)
19V
UVLO
12V/8V
6 OUT
(7)
Delay
Circuit
0.97V/0.9V
2 CS/FB
(3)
Latch/SS
1V
Figure 1. Internal Block Diagram
Note:
1. ( ) is 10-SSOP Pin Number.
© 2008 Fairchild Semiconductor Corporation
FAN7601B • Rev.1.0.2
2
www.fairchildsemi.com