S25FL032P View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
S25FL032P Datasheet PDF : 60 Pages
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S25FL032P
7. Device Operations
All Cypress SPI devices accept and output data in bytes (8 bits at a time). The SPI device is a slave device that supports an inactive
clock while CS# is held low.
7.1 Byte or Page Programming
Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which
consists of four bytes plus data. The Page Program sequence accepts from 1 byte up to 256 consecutive bytes of data (which is the
size of one page) to be programmed in one operation. Programming means that bits can either be left at 0, or programmed from 1 to
0. Changing bits from 0 to 1 requires an erase operation.
7.2 Quad Page Programming
The Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed using 4 pins as inputs at the same
time, thus effectively quadrupling the data transfer rate, compared to the Page Program (PP) instruction. The Write Enable Latch
(WEL) bit must be set to a 1 using the Write Enable (WREN) command prior to issuing the QPP command.
n 7.3 Dual and Quad I/O Mode
ig The S25FL032P device supports Dual and Quad I/O operation when using the Dual/Quad Output Read Mode and the Dual/Quad
es I/O High Performance Mode instructions. Using the Dual or Quad I/O instructions allows data to be transferred to or from the device
D at two to four times the rate of standard SPI devices. When operating in the Dual or Quad I/O High Performance Mode (BBh or EBh
instructions), data can be read at fast speed using two or four data bits at a time, and the 3-byte address can be input two or four
w address bits at a time.
Ne 7.4 Sector Erase / Bulk Erase
r The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to 1. While bits can be
fo individually programmed from 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (SE) or array-wide (BE) level. In addition
d to the 64-KB Sector Erase (SE), the S25FL032P device also offers 4-KB Parameter Sector Erase (P4E) and 8-KB Parameter Sector
e Erase (P8E).
nd 7.5 Monitoring Write Operations Using the Status Register
e The host system can determine when a Write Register, program, or erase operation is complete by monitoring the Write in Progress
m (WIP) bit in the Status Register. The Read from Status Register command provides the state of the WIP bit. In addition, the
m S25FL032P device offers two additional bits in the Status Register (P_ERR, E_ERR) to indicate whether a Program or Erase
o operation was a success or failure.
ec 7.6 Active Power and Standby Power Modes
t R The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the device is disabled, but
o may still be in the Active Power mode until all program, erase, and Write Registers operations have completed. The device then
N goes into the Standby Power mode, and power consumption drops to ISB. The Deep Power-Down (DP) command provides
additional data protection against inadvertent signals. After writing the DP command, the device ignores any further program or
erase commands, and reduces its power consumption to IDP.
Document Number: 002-00650 Rev. *L
Page 11 of 60
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