Connection Diagram
Logic Symbol
Pin Description
Pin
Names
OE
T/R
A0–A7
B0–B7
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Logic Diagram
Truth Table
Inputs
Outputs
OE T/R
L
L Bus B0–B7 Data to Bus A0–A7
L
H Bus A0–A7 Data to Bus B0–B7
H
X HIGH Z State on A0–A7, B0–B7(2)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Note:
2. Unused bus terminals during HIGH Z State must be
held HIGH or LOW.
©2001 Fairchild Semiconductor Corporation
74ALVC245 Rev. 1.3.0
2
www.fairchildsemi.com