PI74VCX16374
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16-Bit D-Type Flip-Flop
with 3-State Outputs
Product Features
• The PI74VCX Family is designed for low voltage
operation, VDD = 1.8V to 3.6V
• 3.6V I/O Tolerant Inputs and Outputs
• Supports Live Insertion
• Balanced Drive, ±24mA
• Uses patented Noise Reduction Circuitry
• Typical VOLP (Output Ground Bounce)
< 0.6V at VDD = 2.5V, TA = 25ºC
• Typical VOHV (Output VOH Undershoot)
< –0.6V at VDD = 2.5V, TA = 25ºC
• Power-Off high impedance inputs and outputs
• Industrial operation at –40°C to +85°C
• Packaging (Pb-free & Green available):
– 48-pin 240 mil. wide plastic TSSOP (A)
Logic Block Diagram
1
1OE
Product Description
The PI74VCX16374 is particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and working registers.
This device can be used as two 8-bit Flip-Flops or one 16-bit flip-
flop. On the positive transition of the clock (CLK) input, the Q
outputs of the flip-flop take on the logic levels set up at the date
(D) inputs.
A buffered Output Enable (OE) input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state in which the outputs neither load
nor drive the bus lines significantly. The high-impedance state
and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not
affect internal operations of the flip-flop. Old data can be retained
or new data can be entered while the outputs are in the high
impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VDD through a pullup resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
The PI74VCX family is I/O Tolerant, allowing it to operate in
mixed 1.8V/3.6V systems.
1CLK 48
>C1
47
1D1
1D
2 1Q1
24
2OE
2CLK 25
36
2D1
To Seven Other Channels
>C1
1D
13 2Q1
To Seven Other Channels
06-0204
1
PS8327B 10/27/06