
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 5.
D0 14
13
D1
DATA
INPUTS
12
D2
D3 11
DATA– DE1 9
ENABLES DE2 10
RESET 15
CLOCK 7
OUTPUT
ENABLES
OE1 1
OE2 2
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT 1 kΩ
CL *
MC74HC173
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
* Includes all probe and jig capacitance
Figure 6.
LOGIC DETAIL
DQ
C
C
R
DQ
C
C
R
DQ
C
C
R
DQ
C
C
R
VCC
3 Q0
VCC
4 Q1
VCC
5 Q2
VCC
6 Q3
High–Speed CMOS Logic Data
5
DL129 — Rev 6
MOTOROLA