TIMING DIAGRAM
MC54/74HC589
SHIFT CLOCK
SERIAL DATA
INPUT, SA
OUTPUT ENABLE
SERIAL SHIFT/
PARALLEL LOAD
LATCH CLOCK
AL
H
BL
L
L
L
L
L
CL
H
L
L
PARALLEL D L
L
DATA
INPUTS
EL
H
L
L
L
H
FL
H
L
H
GL
L
L
L
H
QH
ÉÉÉÉÉ L
H
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ HIGH IMPEDANCE
HL
H
HL
H
HL
HL H
H
LLL
H
SERIAL SHIFT
SERIAL SHIFT
SERIAL SHIFT
L HH
SERIAL
SHIFT
RESET LATCH LOAD LATCH PARALLEL LOAD
AND SHIFT REGISTER
SHIFT REGISTER
LOAD LATCH PARALLEL LOAD PARALLEL LOAD, LATCH
SHIFT REGISTER AND SHIFT REGISTER
High–Speed CMOS Logic Data
3–7
DL129 — Rev 6
MOTOROLA