MC74AC113D View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
MFG CO.
MC74AC113D Datasheet PDF : 6 Pages
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MC74AC113
MC74ACT113
Dual JK Negative
EdgeĆTriggered FlipĆFlop
The MC74AC113/74ACT113 consists of two high-speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise and fall
times of the clock waveform. The JK design allows operation as a D flip-flop (refer to
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
Set is independent of clock
• Outputs Source/Sink 24 mA
• ′ACT113 Has TTL Compatible Inputs
CONNECTION DIAGRAM
DUAL JK NEGATIVE
EDGE-TRIGGERED
FLIP-FLOP
N SUFFIX
CASE 646-06
PLASTIC
VCC CP2 K2
14 13 12
J2 SD2 Q2 Q2
11 10 9 8
J
CP
SD
Q
K
Q
K
Q
CP
J
SD
Q
12
CP1 K1
345
J1 SD1 Q1
67
Q1 GND
D SUFFIX
CASE 751A-03
PLASTIC
LOGIC SYMBOL
4
10
MODE SELECT — TRUTH TABLE
Operating Mode
Set
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
Inputs
SD
J
K
L
X
X
H
h
h
H
l
h
H
h
l
H
l
l
Outputs
Q
Q
H
L
q
q
L
H
H
L
q
q
H, h = HIGH Voltage Level
L, l = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input
(or output) one set-up time prior to the HIGH to LOW clock transition.
SD
SD
3
J
Q 5 11
J
Q9
1 CP
13 CP
2K
Q 6 12 K
Q8
VCC = PIN 14
GND = PIN 7
FACT DATA
5-1
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