CS62180B-IL View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS62180B-IL

T1 Framer

Cirrus Logic 

CS62180B

RFER - Receive Frame Error, Pin 38 (PLCC, Pin 42).

Transitions high with the output of an errored framing bit, and is held for 2 bit periods. FT and

FS bits are tested in 193S and SLC-96® modes, and FPS bits are tested in 193E. In T1DM

mode, the FS, FT and channel 24 sync bits are tested. Also signals CRC errors in 193E mode,

by going high 1/2 bit before the next extended superframe, and holding for 1 period (from

falling edge of RCLK to next falling edge).

RLOS - Receive Loss of Sync, Pin 39 (PLCC, Pin 43).

Transitions high during receiver resync, low otherwise. Transitions high when receiver begins a

resync, and falls low one frame after new timing is declared.

RSER - Receive Serial Data, Pin 26 (PLCC, Pin 30).

Received data, output in NRZ format. Data on RSER is valid and stable on the falling edges of

RCLK. Delay from RPOS/RNEG to RSER is 13 RCLK periods.

RABCD - Receive ABCD Signaling, Pin 29 (PLCC, Pin 33).

Signaling data extracted from LSB of DS0 channels during signaling frames is valid on

RABCD during corresponding channel output on RSER (LSB is available on RABCD seven bit

periods before it appears at RSER). During non-signaling frames, RABCD continues to output

LSB concurrently with word on RSER. After update, data on RABCD is valid and stable on

the falling edge of RCLK.

RLINK - Receive Link Data, Pin 22 (PLCC, Pin 24).

In 193S mode, S-bit data is output on RLINK one RCLK prior to start of corresponding even

frame, and held for 2 frames until next update. In 193E mode, FDL data is output on RLINK

one RCLK prior to start of corresponding odd frame, and held for 2 frames until next update.

After update, data on RLINK is valid and stable on the falling edge of RCLK.

In SLC-96® mode, all Fs and DL bits are output on RLINK using RLCLK. In T1DM mode,

channel 24 "A" link data is output on RLINK, and is valid and stable on the falling edge of

RFSYNC.

RLCLK - Receive Link Clock, Pin 23 (PLCC, Pin 26).

RLCLK runs at 4 kHz with a 50% duty cycle. It’s high during odd numbered frames. RCLK is

useful for marking S-bit, DL or FDL channel timing, output on RLINK. RLCLK is present,

but serves no useful purpose in the T1DM mode.

RCHCLK - Receive Channel Clock, Pin 25 (PLCC, Pin 29).

192 kHz clock which identifies DS0 channel boundaries output on RSER. RCHCLK is useful

for parallel to serial conversion of DS0 channel data.

RFSYNC - Receive Frame Sync, Pin 27 (PLCC, Pin 31).

Goes high for one RCLK period concurrent with the F-bit of each new frame output on RSER,

low otherwise. In the T1DM mode, the falling edge of RFSYNC can be used to sample the "A"

link channel on RLINK.

DS225PP2

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