Philips Semiconductors
4-bit synchronous binary counter with
synchronous reset
Product specification
HEF40163B
MSI
Fig.3 Pinning diagram.
PINNING
PE
P0 to P3
CEP
CET
CP
SR
O0 to O3
TC
parallel enable input
parallel data inputs
count enable parallel input
count enable trickle input
clock input (LOW to HIGH, edge-triggered)
synchronous reset input (active LOW)
parallel outputs
terminal count output
HEF40163BP(N): 16-lead DIL; plastic (SOT38-1)
HEF40163BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF40163BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
SYNCHRONOUS MODE SELECTION
TERMINAL COUNT GENERATION
SR PE CEP CET
MODE
CET
(O0 ⋅ O1 ⋅ O2 ⋅ O3)
TC
H
L
X
X preset
L
L
L
H
H
L
X no change
L
H
L
H
H
X
L no change
H
L
L
H
H
H
H count
H
H
H
L
X
X
X reset
Note
Notes
1. H = HIGH state (the more positive voltage)
1. TC = CET ⋅ O0 ⋅ O1 ⋅ O2 ⋅ O3
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
January 1995
Fig.4 State diagram.
4