IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
tCLKH
tCLK
RCLK
tENS
tENH
tCLKL
REN
NO OPERATION
tREF
EF
tA
Q0 - Q7
OE
tOLZ
tOE
WCLK
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tREF
VALID DATA
tOHZ
tSKEW1(1)
WEN
2680 drw 06
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the curent clock cycle. If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 4. Read Cycle Timing
5.12
9