ISP1583ET View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

ISP1583ET

Hi-Speed USB peripheral controller

NXP Semiconductors. 

NXP Semiconductors

ISP1583

Hi-Speed USB peripheral controller

Table 21. Register overview …continued

Name

Destination

Task File 1F0

ATAPI peripheral

Task File 1F1

Task File 1F2

Task File 1F3

Task File 1F4

Task File 1F5

Task File 1F6

Task File 1F7

ATAPI peripheral

ATAPI peripheral

ATAPI peripheral

ATAPI peripheral

ATAPI peripheral

ATAPI peripheral

ATAPI peripheral

Task File 3F6

Task File 3F7

DMA Interrupt Reason

ATAPI peripheral

ATAPI peripheral

DMA controller

DMA Interrupt Enable

DMA controller

DMA Endpoint

DMA controller

DMA Strobe Timing

DMA controller

DMA Burst Counter

DMA controller

General registers

Interrupt

device

Chip ID

device

Frame Number

device

Scratch

Unlock Device

Test Mode

device

device

PHY

Address Description

Size

(bytes)

40h

single address word register: byte 0 2

(lower byte) is accessed first

48h

IDE device access

1

49h

IDE device access

1

4Ah

IDE device access

1

4Bh

IDE device access

1

4Ch

IDE device access

1

4Dh

IDE device access

1

44h

IDE device access (write only; reading 1

returns FFh)

4Eh

IDE device access

1

4Fh

IDE device access

1

50h

shows reason (source) for DMA

2

interrupt

54h

enables DMA interrupt sources

2

58h

selects endpoint FIFO, data flow

1

direction

60h

strobe duration in MDMA mode

1

64h

DMA burst length

2

Reference

Section 9.4.5

on page 53

Section 9.4.6

on page 56

Section 9.4.7

on page 57

Section 9.4.8

on page 57

Section 9.4.9

on page 58

Section 9.4.10

on page 59

18h

shows interrupt sources

4

70h

product ID code and hardware version 3

74h

last successfully received

2

Start-Of-Frame: lower byte (byte 0) is

accessed first

78h

allows save or restore of firmware

2

status during suspend

7Ch

re-enables register write access after 2

suspend

84h

direct setting of the DP and DM

1

states, internal transceiver test (PHY)

Section 9.5.1

on page 59

Section 9.5.2

on page 61

Section 9.5.3

on page 62

Section 9.5.4

on page 62

Section 9.5.5

on page 63

Section 9.5.6

on page 63

9.1 Register access

Register access depends on the bus width used:

• 8-bit bus: multi-byte registers are accessed lower byte (LSByte) first

• 16-bit bus: for single-byte registers, the upper byte (MSByte) must be ignored

Endpoint specific registers are indexed using the Endpoint Index register. The target

endpoint must be selected before accessing the following registers:

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

© NXP B.V. 2008. All rights reserved.

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