µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
TIn Input Timing (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
TIn0, TIn1 (n = 00, 01)
high-level width
tTIH
<58>
2Tsam + 20Note
ns
TIn (n = 2 to 7, 10, 11)
high-level width
3/fXX + 20
ns
TIn0, TIn1 (n = 00, 01)
low-level width
tTIL
<59>
2Tsam + 20Note
ns
TIn (n = 2 to 7, 10, 11)
low-level width
3/fXX + 20
ns
Note Tsam can be selected by setting the PRMn1 and PRMn0 bits of prescaler mode registers n0, n1 (PRMn0,
PRMn1) (n = 0, 1).
TM0 (PRM00, PRM01 registers): Tsam = 2/fXX, 4/fXX, 16/fXX, 64/fXX, 256/fXX, 1/INTWTI period
TM1 (PRM10, PRM11 registers): Tsam = 2/fXX, 4/fXX, 16/fXX, 32/fXX, 128/fXX, 256/fXX
However, when the TIn0 valid edge is selected as the count clock, Tsam = 4/fXX (n = 0, 1).
<58>
TIn
Remark n = 000, 001, 010, 011, 10, 11, 2 to 7
<59>
Preliminary Data Sheet U13953EJ1V0DS00
31