LTC6803 View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC6803

Multicell Battery Stack Monitor

Linear Technology 

LTC6803-1/LTC6803-3

OPERATION

Table 13. Memory Bit Descriptions (continued)

NAME DESCRIPTION

VALUES

MCxI

Mask Cell x Interrupts

x = 1..12 0 = enable interrupts for cell ‘x’ (default)

1 = turn off interrupts and clear flags for cell ‘x’

CxV

Cell x Voltage*

x = 1..12 12-bit ADC measurement value for cell ‘x’

cell voltage for cell ‘x’ = (CxV – 512) • 1.5mV

reads as 0xFFF while A/D conversion in progress

CxUV Cell x Undervoltage Flag

x = 1..12 cell voltage compared to VUV comparison voltage

0 = cell ‘x’ not flagged for undervoltage condition; 1 = cell ‘x’ flagged

CxOV Cell x Overvoltage Flag

x = 1..12 cell voltage compared to VOV comparison voltage

0 = cell ‘x’ not flagged for overvoltage condition; 1 = cell ‘x’ flagged

ETMPx External Temperature Measurement* Temperature measurement voltage = (ETMPx – 512) • 1.5mV

THSD Thermal Shutdown Status

0 = thermal shutdown has not occurred; 1 = thermal shutdown has occurred

Status cleared to ‘0’ on read of Thermal Register Group

REV

Revision Code

Device revision code

ITMP Internal Temperature Measurement* Temperature measurement voltage = (ITMP – 512) • 1.5mV = 8mV * T(°K)

PEC

Packet Error Code

Cyclic redundancy check (CRC) value

REF

Reference Voltage for Diagnostics

This reference voltage = (REF – 512) • 1.5mV. Normal range is within 2.1V to 2.9V

*Voltage equations use the decimal value of the registers, 0 to 4095 for 12-bit and 0 to 255 for 8-bit registers

SERIAL COMMAND EXAMPLES

Examples below use a configuration of three stacked

LTC6803-1 or LTC6803-3 devices: bottom (B), middle

(M), and top (T)

Write Configuration Registers (Figure 8)

1. Pull CSBI low

2. Send WRCFG command and its PEC byte

3. Send CFGR0 byte for top device, then CFGR1 (T), …CFGR5 (T), PEC of CFGR0(T) to CFGR5(T)

4. Send CFGR0 byte for middle device, then CFGR1 (M) … CFGR5 (M) ), PEC of CFGR0(M) to CFGR5(M)

5. Send CFGR0 byte for bottom device, then CFGR1 (B), … CFGR5 (B) ), PEC of CFGR0(B) to CFGR5(B)

6. Pull CSBI high; data latched into all devices on rising edge of CSBI. S pins respond as data latched.

Calculation of serial interface time for sequence above:

Number of devices in stack = N

Number of bytes in sequence = B = 2 command byte and 7 data bytes per device = 2 + 7 • N

Serial port frequency per bit = F

Time = (1/F) • B • 8 bits/byte = (1/F) • (2 + 7 • N) • 8

Time for 3-cell example above, with 1MHz serial port = (1/1000000) • (2 + 7 • 3) • 8 = 184µs

680313f

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