MT46V16M16TG-75Z View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
MT46V16M16TG-75Z Datasheet PDF : 80 Pages
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256Mb: x4, x8, x16
DDR SDRAM
CK#
CK1
CKE
COMMAND2
T0
T11
tCH
tIS tIH
tCL
tIS
tIS tIH
NOP
AR
ADDR
Figure 47: Self Refresh Mode
Ta01
Ta1
((
))
((
))
tCK
tIS
((
))
((
))
NOP
((
))
Ta2
((
))
((
))
((
))
((
))
((
))
NOP
((
))
((
((
))
))
((
((
))
))
((
((
DQS
))
))
((
((
))
))
((
((
DQ
))
((
))
((
))
))
((
DM
))
((
))
((
))
((
))
tRP4
Enter Self Refresh Mode7
tXSNR5
tXSRD6
Exit Self Refresh Mode7
Tb1
VALID3
tIS tIH
VALID
Tb2
((
))
((
))
((
))
((
))
((
))
VALID
((
))
((
VALID
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Tc1
VALID
VALID
DON’T CARE
NOTE:
1. Clock must be stable until after the SELF REFRESH command has been registered. A change in clock frequency is allowed before
Ta0, provided it is within the specified tCK limits. Regardless, the clock must be stable before exiting self refresh mode. That is,
the clock must be cycling within specifications by Ta0.
2. NOPs are interchangeable with DESELECT commands; AR = AUTO REFRESH command.
3. Auto refresh is not required at this point, but is highly recommended.
4. Device must be in the all banks idle state prior to entering self refresh mode.
5. tXSNR is required before any non-READ command can be applied; only NOP or DESELECT commands are allowed until Tb1.
6. tXSRD (200 cycles of a valid CK and CKE = high) is required before any READ command can be applied.
7. As a general rule, any time self refresh mode is exited, the DRAM may not re-enter the self refresh mode until all rows have
been refreshed via the AUTO REFRESH command at the distributed refresh rate, tREFI, or faster. However, self refresh mode
may be re-entered anytime after exiting, if the following conditions are all met:
a. The DRAM had been in the Self Refresh Mode for a minimum of 200ms prior to exiting.
b. tXSNR and tXSRD are not violated.
c. At least two AUTO REFRESH commands are performed during each tREFI interval while the DRAM remains out of
Self Refresh mode.
8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.
9. Once initialized, VREF must always be powered within the specified range.
SYMBOL
tCH
tCL
tCK (2.5)
tCK (2)
tIHF
tISF
-6/6T/6T
MIN MAX
0.45 0.55
0.45 0.55
6
13
7.5 13
0.75
0.75
-75E/75Z
MIN MAX
0.45 0.55
0.45 0.55
7.5 13
7.5 13
0.90
0.90
-75
MIN MAX
0.45 0.55
0.45 0.55
7.5
13
10
13
0.90
0.90
UNITS
tCK
tCK
ns
ns
ns
ns
SYMBOL
tIHS
tISS
tRFC
tRP
tVTD
-6/6T/6T
MIN MAX
0.8
0.8
72
18
0
-75E/75Z
MIN MAX
1
1
75
15
0
-75
MIN MAX
1
1
75
20
0
UNITS
ns
ns
ns
ns
ns
09005aef8076894f
256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN
72
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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