CK#
CK
COMMAND
ADDRESS
DQS
DQ
CK#
CK
COMMAND
ADDRESS
T0
READ
Bank a,
Col n
T0
READ
Bank a,
Col n
DQS
DQ
256Mb: x4, x8, x16
DDR SDRAM
Figure 13: READ Burst
T1
T2 T2n T3 T3n T4
T5
NOP
NOP
NOP
NOP
NOP
CL = 2
DO
n
T1
T2 T2n T3 T3n T4
T5
NOP
NOP
NOP
NOP
NOP
CL = 2.5
DO
n
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DO n = data-out from column n.
2. Burst length = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
09005aef8076894f
256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.