FIS1100 View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
MFG CO.
FIS1100
Fairchild Semiconductor
FIS1100 Datasheet PDF : 55 Pages
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1.5 Package & Pin Information
RESV3 1
VDDa 2
GNDa 3
RESV2 4
FIS1100
Top Through View
NC
12 INT1/CLKout
11 INT2/DRDY
10 CS
9 SA0/SDO
INT1/CLKout 12
INT2/DRDY 11
CS 10
SA0/SDO 9
FIS1100
Bottom View
NC
1 RESV3
2 VDDa
3 GNDa
4 RESV2
Figure 4. Pins Face Down (Top View)
Do Not Solder Center Pin (NC)
Table 2. Pin Definitions
Figure 5. Pins Face Up (Bottom View)
Do Not Solder Center Pin (NC)
Pin # Name Alternate Name Alternate Name
Description
1
RESV3
Reserved. Connect to Board Ground (GND)
2
VDDa
Power Supply for Analog
3
GNDa
Ground for Analog
4
RESV2
Reserved. No Connection (NC)
5
RESV1
6
SDA2
7
SCL2
Reserved. No Connection (NC)
Master I2C Serial Data
Master I2CSerial Clock
8
9
10(1)
VDDd
SA0(1)(3)
CS
SDO
Power Supply for Digital and IO Pins
Host I2C Slave Address LSB (SA0);
Host 4-Wire SPI Serial Data Output (SDO)
Host SPI Chip Select (1 = I2C Mode). See SPI
Mode Configuration section
11
INT2
DRDY
Interrupt2. Data Ready/FIFO Interrupt
12
INT1
13
SDA
14
SCL
CLKout
SDI(2)(3)
SPC(2)(3)
SDIO(2)(3)
Interrupt1. General Purpose Interrupt. Clock out in
OIS Mode
Host I2C Serial Data (SDA);
Host 4-Wire SPI Serial Data Input (SDI);
Host 3-Wire SPI Serial Data Output (SDIO)
Host I2C Serial Clock (SCL);
Host SPI Serial Clock (SPC)
15
GNDd
Ground
16
RST ***
Reset Input. Assert for at least 5 s. Part ready for
communication 50 s after assertion. After RST,
the device will go through its boot process, please
refer to Table 7 and Table 8 for wakeup times.
Notes:
1. This pin has an internal 200 K pull up resistor.
2. In SPI mode (not in I2C Mode), there is an internal pull down 200 K resistor.
3. Refer to Section 1 for detailed configuration information.
© 2015 Fairchild Semiconductor Corporation
FIS1100 • Rev. 1.2
6
www.fairchildsemi.com
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