dsPIC33FJXXXGPX06A/X08A/X10A
FIGURE 1-1:
PSV and Table
Data Access
Control Block
dsPIC33FJXXXGPX06A/X08A/X10A GENERAL BLOCK DIAGRAM
Y Data Bus
Interrupt
Controller
23
23
23
Address Latch
8
16
PCU PCH PCL
Program Counter
Stack
Control
Logic
Loop
Control
Logic
X Data Bus
16
16
Data Latch
16
Data Latch
X RAM
Address
Latch
Y RAM
Address
Latch
16
16
DMA
RAM
DMA
Controller
Address Generator Units
PORTA
PORTB
16
PORTC
Program Memory
Data Latch
24
Instruction
Decode and
Control
Control Signals
to Various Blocks
OSC2/CLKO Timing
OSC1/CLKI Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
VCAP
VDD, VSS MCLR
ROM Latch
EA MUX
16 16
Instruction Reg
16
DSP Engine
Divide Support
16 x 16
W Register Array
16
16-bit ALU
16
Timers
OC/
DCI
1-9
PWM1-8
ADC1,2
ECAN1,2
PORTD
PORTE
PORTF
PORTG
IC1-8
CN1-23
SPI1,2
I2C1,2
UART1,2
Note:
Not all pins or features are implemented on all device pinout configurations. See the “Pin Diagrams” section for the
specific pins and features present on each device.
DS70593C-page 22
© 2011 Microchip Technology Inc.