ADAU1452/ADAU1451/ADAU1450
Data Sheet
SPI Interface—Slave
TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 10% to 3.3 V + 10%.
Table 14.
Parameter
SPI SLAVE PORT
fSCLKWRITE
fSCLKREAD
tSCLKPWL
tSCLKPWH
tSSS
tSSH
tSSPWH
tSSPWL
tMOSIS
tMOSIH
tMISOD
Min
6
21
1
2
10
10
1
2
Max
Unit Description
22
MHz SCLK write frequency
22
MHz SCLK read frequency
ns SCLK pulse width low, SCLK = 22 MHz
ns SCLK pulse width high, SCLK = 22 MHz
ns SS setup to SCLK rising edge
ns SS hold from SCLK rising edge
ns SS pulse width high
ns SS pulse width low; minimum low pulse width for SS when
entering SPI mode by toggling the SS pin three times
ns MOSI setup to SCLK rising edge
ns MOSI hold from SCLK rising edge
39
ns MISO valid output delay from SCLK falling edge
SS
SCLK
MOSI
MISO
tSSS
tSCLKPWH
tMOSIS
tMOSIH
tSCLKPWL
Figure 9. SPI Slave Port Timing Specifications
tSSH
tSSPWH
tMISOD
Rev. C | Page 14 of 180