AD5308(RevB) View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD5308
(Rev.:RevB)
(Rev.:RevB)
Analog Devices
AD5308 Datasheet PDF : 19 Pages
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AD5308/AD5318/AD5328
AC CHARACTERISTICS1
Parameter2
(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless
otherwise noted.)
A, B Version3
Min Typ Max
Unit
Conditions/Comments
Output Voltage Settling Time
AD5308
AD5318
AD5328
Slew Rate
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
6
8
7
9
8
10
0.7
12
0.5
0.5
1
3
200
–70
NOTES
1Guaranteed by design and characterization; not production tested.
2See the Terminology section.
3Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.
Specifications subject to change without notice.
µs
µs
µs
V/µs
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
VREF = VDD = 5 V
1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
1/4 Scale to 3/4 Scale Change (0x100 to 0x300)
1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)
1 LSB Change around Major Carry
VREF = 2 V ± 0.1 V p-p. Unbuffered Mode.
VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz.
TIMING CHARACTERISTICS1, 2, 3
Parameter
A, B Version
Limit at TMIN, TMAX
Unit
Conditions/Comments
t1
33
t2
13
t3
13
t4
13
t5
5
t6
4.5
t7
0
t8
50
t9
20
t10
20
t11
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
LDAC Pulsewidth
SCLK Falling Edge to LDAC Rising Edge
SCLK Falling Edge to LDAC Falling Edge
NOTES
1Guaranteed by design and characterization; not production tested.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (VIL + VIH)/2.
3See Figures 2 and 3.
Specifications subject to change without notice.
t1
SCLK
SYNC
DIN
LDAC1
t8
t4
t3
t6
t5
DB15
t2
t7
DB0
t9
t11
t10
LDAC2
REV. B
NOTES
1 ASYNCHRONOUS LDAC UPDATE MODE
2 SYNCHRONOUS LDAC UPDATE MODE
Figure 1. Serial Interface Timing Diagram
–3–
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