ADP3181JRQZ-RL View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
ADP3181JRQZ-RL Datasheet PDF : 24 Pages
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ADP3181
Table 5. VR 10 VID Codes for the ADP3181, CPUID Used as a VID5 Input
VID4
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
VID3
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
VID2
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
VID1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
VID0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
CPUID
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
No CPU
No CPU
0.8375 V
0.8500 V
0.8625 V
0.8750 V
0.8875 V
0.9000 V
0.9125 V
0.9250 V
0.9375 V
0.9500 V
0.9625 V
0.9750 V
0.9875 V
1.0000 V
1.0125 V
1.0250 V
1.0375 V
1.0500 V
1.0625 V
1.0750 V
1.0875 V
1.1000 V
1.1125 V
1.1250 V
1.1375 V
1.1500 V
1.1625 V
1.1750 V
1.1875 V
1.2000 V
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VID2
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
VID1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
VID0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
CPUID
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
1.2125 V
1.2250 V
1.2375 V
1.2500 V
1.2625 V
1.2750 V
1.2875 V
1.3000 V
1.3125 V
1.3250 V
1.3375 V
1.3500 V
1.3625 V
1.3750 V
1.3875 V
1.4000 V
1.4125 V
1.4250 V
1.4375 V
1.4500 V
1.4625 V
1.4750 V
1.4875 V
1.5000 V
1.5125 V
1.5250 V
1.5375 V
1.5500 V
1.5625 V
1.5750 V
1.5875 V
1.6000 V
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3181 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 6. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, then divide the master clock by 3 for the
frequency of the remaining phases. If PWM3 and 4 are
grounded, divide by 2. If all phases are in use, divide by 4.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3181 combines differential sensing with a high
accuracy VID DAC and reference and a low offset error
amplifier to maintain a worst-case specification of ±14.5 mV
differential sensing error over its full operating output voltage
and temperature ranges. The output voltage is sensed between
the FB and FBRTN pins. FB should be connected through a
resistor to the regulation point, usually the remote sense pin of
the microprocessor. FBRTN should be connected directly to the
remote sense ground point. The internal VID DAC and
precision reference are referenced to FBRTN, which has a
minimal current of 100 µA to allow accurate remote sensing.
The internal error amplifier compares the output of the DAC to
the FB pin to regulate the output voltage.
Rev. 0 | Page 10 of 24
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