AD7884BQ View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

AD7884BQ

LC2MOS 16-Bit, High Speed Sampling ADCs

Analog Devices 

AD7884/AD7885

AD7884 to ADSP-2101 Interface

Figure 21 shows an interface between the AD7884 and the

ADSP-2101. Conversion is initiated using a timer that allows

very accurate control of the sampling instant. The AD7884 BUSY

line provides an interrupt to the ADSP-2101 when conversion is

completed. The RD pulsewidth of the processor can be programmed

using the Data Memory Wait State Control register. The result

can then be read from the ADC using the following instruction:

MR0 = DM (ADC)

where MR0 is the ADSP-2101 MR0 register, and ADC is the

AD7884 address.

TIMER

DMA13–DMA0

ADDRESS BUS

ADSP-2101

DMS

IRQn

RD

ADDRESS

DECODE LOGIC

EN

AD7884

CONVST

CS

BUSY

RD

DMD15–DMD0

DATA BUS

DB15–DB0

Figure 21. AD7884 to ADSP-2101 Interface

Standalone Operation

If CS and RD are tied permanently low on the AD7884, then,

when a conversion is completed, output data will be valid on the

rising edge of BUSY. This makes the device very suitable for

standalone operation. All that is required to run the device is an

external CONVST pulse that can be supplied by a sample timer.

Figure 22 shows the AD7884 set up in this mode with the BUSY

signal providing the clock for the 74HC574 three-state latches.

A0

HBEN

CONVST

TIMER

DB15–DB8

74HC574

AD7884

CLK

DB7–DB0

74HC574

BUSY

CS

RD

CLK

Figure 22. Standalone Operation

Digital Feedthrough from an Active Bus

It is very important when using the AD7884/AD7885 in a

microprocessor based system to isolate the ADC data bus from

the active processor bus while a conversion is being executed.

This yields the best noise performance from the ADC. Latches

like the 74HC574 can be used to do this. If the device is connected

directly to an active bus, then the converter noise typically increases

by a factor of 30%.

–14–

REV. E

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