Nexperia
74HC4002-Q100; 74HCT4002-Q100
Dual 4-input NOR gate
4. Functional diagram
$
%
&
'
$
%
&
'
<
<
DDD
Fig 1. Functional diagram
$
%
&
'
$
%
&
'
Fig 2. Logic symbol
<
<
DDD
DDD
Fig 3. IEC Logic symbol
5. Pinning information
5.1 Pinning
$
%
&
'
Fig 4. Logic diagram
<
DDD
+&4
+&74
<
$
%
&
'
QF
*1'
9&&
<
'
&
%
$
QF
DDD
Fig 5. Pin configuration SOT108-1
+&4
<
$
%
&
'
QF
*1'
9&&
<
'
&
%
$
QF
DDD
Fig 6. Pin configuration SOT402-1
74HC_HCT4002_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 July 2012
© Nexperia B.V. 2017. All rights reserved
2 of 14