Nexperia
74HC160
Presettable synchronous BCD decade counter; asynchronous reset
9,
W:
QHJDWLYH
SXOVH
90
9
WI
9,
SRVLWLYH
SXOVH
WU
90
9
W:
90
WU
WI
90
9,
*
9&&
92
'87
57
9&&
5/ 6
&/
RSHQ
DDG
Test data is given in Table 9.
Test circuit definitions:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistance.
S1 = Test selection switch
Fig 14. Test circuit for measuring switching times
Table 9. Test data
Input
VI
tr, tf
VCC
6 ns
Load
CL
15 pF, 50 pF
RL
1 k
S1 position
tPHL, tPLH
open
74HC160
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 September 2016
© Nexperia B.V. 2017. All rights reserved
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