SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
RAS
tw(RL)
tc(rd)
CAS
tt
td(RLCL)
td(CLRH)
td(RLCH)
tw(CL)
td(RLCA)
th(RA)
tsu(RA)
th(RLCA)
tsu(CA)
td(CACH)
td(CARH)
tw(RH)
td(CHRL)
tw(CH)
A0 – A9
Row
Column
Don’t Care
W
Don’t Care
tsu(rd)
th(CA)
th(RHrd)
th(CHrd)
Don’t Care
ta(CA)
ta(C)
tdis(CH)
Q
Hi-Z
See Note A
Valid
ta(R)
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 2. Read-Cycle Timing
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
11