ADUC7033 View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

ADUC7033

Integrated, Precision Battery Sensor for Automotive

Analog Devices 

ADuC7033

Parameter

MCU START-UP TIME

At Power-On

After Reset Event

From MCU Power-Down

Oscillator Running

Wake Up from Interrupt

Wake Up from LIN

Crystal Powered Down

Wake Up from Interrupt

Internal PLL Lock Time

LIN INPUT/OUTPUT GENERAL

Baud Rate

VDD

Input Capacitance

Input Leakage Current

LIN Comparator Response Time1

ILIN DOM MAX

ILIN_PAS_REC

ILIN1

ILIN_PAS_DOM1

ILIN_NO_GND29

VLIN_DOM1

VLIN_REC1

VLIN_CNT1

VHYS1

VLIN_DOM_DRV_LOSUP1

RL 500 Ω

RL 1000 Ω

VLIN_DOM_DRV_HISUP1

RL 500 Ω

RL 1000 Ω

VLIN_RECESSIVE

VBAT Shift29

GND Shift29

RSLAVE

VSERIAL DIODE29

Symmetry of Transmit

Propagation Delay1

Receive Propagation Delay1

Symmetry of Receive Propagation

Delay1

LIN VERSION 2.0 SPECIFICATION

D1

Test Conditions/Comments

Includes kernel power-on execution time

Includes kernel power-on execution time

Bus load conditions (CBUS||RBU): 1 nF||1 kΩ,

6.8 nF||660 Ω; 10 nF||500 Ω

Supply voltage range at which the LIN interface is

functional

Input (low) = IO_VSS

Using 22 Ω resistor

Current limit for driver when LIN bus is in

dominant state, VBAT = VBAT (MAX)

Driver off, 7.0 V < VLIN < 18 V, VDD = VLIN − 0.7 V

VBAT disconnected, VDD = 0 V, 0 < VLIN < 18 V

Input leakage VLIN = 0 V

Control unit disconnected from ground,

GND = VDD, 0 V < VLIN < 18 V, VBAT = 12 V

LIN receiver dominant state, VDD > 7.0 V

LIN receiver recessive state, VDD > 7.0 V

LIN receiver center voltage, VDD > 7.0 V

LIN receiver hysteresis voltage

LIN dominant output voltage, VDD = 7 V

LIN dominant output voltage, VDD = 18 V

LIN recessive output voltage

Slave termination resistance

Voltage drop at the Serial Diode DSer_Int

VDD (MIN) = 7 V

VDD (MIN) = 7 V

VDD (MIN) = 7 V

Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ,

6.8 nF||660 Ω; 10 nF||500 Ω

Duty Cycle 1,

THREC(MAX) = 0.744 × VBAT,

THDOM(MAX) = 0.581 × VBAT,

VSUP = 7.0 V . . . 18 V, tBIT = 50 μs,

D1 = tBUS_REC(MIN)/(2 × tBIT)

Min

Typ

25

5

2

2

500

1

1000

7

5.5

−800

38

40

−20

−1

−1

0.6 VDD

0.475 VDD 0.5 VDD

0.6

0.8

0.8 VDD

0

0

20

30

0.4

0.7

−2

−2

0.396

Max

Unit

ms

ms

ms

ms

ms

ms

20,000

18

Bits/sec

V

pF

−400

μA

90

μs

200

mA

+20

μA

10

μA

mA

+1

mA

0.4 VDD V

V

0.525 VDD V

0.175 VDD V

1.2

V

V

2

V

V

V

0.1 VDD V

0.1 VDD V

47

kΩ

1

V

+2

μs

6

μs

+2

μs

Rev. B | Page 7 of 140

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