TC74
SMBUS Read Timing Diagram
A
B
C
D
EF
G
tLOW tHIGH
SCLK
SDA
H
I
JK
tSU(START) tH(START)
tSU-DATA
A = Start Condition
B = MSB of Address Clocked into Slave
C = LSB of Address Clocked into Slave
D = R/W Bit Clocked into Slave
E = Slave Pulls SDA Line Low
F = Acknowledge Bit Clocked into Master
G = MSB of Data Clocked into Master
H = LSB of Data Clocked into Master
tSU(STOP) tIDLE
I = Acknowledge Clock Pulse
J = Stop Condition
K = New Start Condition
SMBUS Write Timing Diagram
A
B
C
D
EF
G
tLOW tHIGH
SCLK
SDA
H
IJ
K
LM
tSU(START) tH(START)
tSU-DATA
tH-DATA
tSU(STOP) tIDLE
A = Start Condition
B = MSB of Address Clocked into Slave
C = LSB of Address Clocked into Slave
D = R/W Bit Clocked into Slave
E = Slave Pulls SDA Line Low
F = Acknowledge Bit Clocked into Master J = Acknowledge Clocked into Master
G = MSB of Data Clocked into Slave K = Acknowledge Clock Pulse
H = LSB of Data Clocked into Slave
L = Stop Condition, Data Executed by Slave
I = Slave Pulls SDA Line Low
M = New Start Condition
FIGURE 1-1:
Timing Diagrams.
DS21462D-page 4
2001-2012 Microchip Technology Inc.