AD7091R-8BRUZ-RL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7091R-8BRUZ-RL7 Datasheet PDF : 42 Pages
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Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Conversion Time: CONVST Falling Edge to Data Available
Acquisition Time
Time Between Conversions (Normal Mode)
CONVST Pulse Width
SCLK Period (Normal Mode)
VDRIVE Above 2.7 V
VDRIVE Above 1.8 V
SCLK Period (Chain Mode)
VDRIVE Above 2.7 V
VDRIVE Above 1.8 V
SCLK Low Time
SCLK High Time
SCLK Falling Edge to Data Remains Valid
SCLK Falling Edge to Data Valid Delay
VDRIVE Above 4.5 V
VDRIVE Above 3.3 V
VDRIVE Above 2.7 V
VDRIVE Above 1.8 V
End of Conversion to CS Falling Edge
CS Low to SDO Enabled
CS High or Last SCLK Falling Edge to SDO High Impedance
SDI Data Setup Time Prior to SCLK Rising Edge
SDI Data Hold Time After SCLK Rising Edge
Last SCLK Falling Edge to Next CONVST Falling Edge
RESET Pulse Width
RESET Pulse Delay Upon Power Up
Time Between Conversions (Power On Software Reset)
Symbol
tCONVERT
tACQ
tCYC
tCNVPW
tSCLK
tSCLK
tSCLKL
tSCLKH
tHSDO
tDSDO
Min
400
1000
10
16
22
20
25
6
6
5
tEOCCSL
5
tEN
tDIS
tSSDISCLK
5
tHSDISCLK
2
tQUIET
50
tRESETPW
10
tRESET_DELAY
50
tCYC_RESET
2
Typ
Max
600
500
12
13
14
20
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
500µA
IOL
TO SDO
20pCFL
500µA
IOH
1.4V
Figure 2. Load Circuit for Digital Interface Timing
X% VDRIVE
Y% VDRIVE
tDELAY
tDELAY
VIH2
VIL2
VIH2
VIL2
NOTES
12FMOINRIMVUDRMIVVEIH≤
3.0V, X = 90 AND Y
AND MAXIMUM VIL
= 10; FOR VDRIVE > 3.0V, X = 70 AND Y = 30.
USED. SEE SPECIFICATIONS FOR DIGITAL
INPUTS PARAMETER IN TABLE 2.
Figure 3. Voltage Levels for Timing
Rev. C | Page 5 of 42
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