MPC5200CVR466BR2 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
MPC5200CVR466BR2 Datasheet PDF : 72 Pages
| |||
SCK
( CLKPOL = 0 )
Output
SCK
( CLKPOL = 1 )
Output
SS
Output
1
10
9
2
2
9
10
3
7
8
MOSI
Output
MISO
Input
4
5
6
Figure 34. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1)
Table 39. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)
Sym
Description
Min
Max
1
Cycle time
4
1024
2
Clock high or low time
2
512
3
Slave select to clock delay
15.0
—
4
Output data valid
—
50.0
5
Input Data setup time
50.0
—
6
Input Data hold time
0.0
—
7
Slave disable lag time
15.0
—
8
Sequential Transfer delay
1
—
1 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
Units
SpecID
IP-Bus Cycle(1) A11.31
IP-Bus Cycle(1) A11.32
ns
A11.33
ns
A11.34
ns
A11.35
ns
A11.36
ns
A11.37
IP-Bus Cycle(1) A11.38
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5200B Data Sheet, Rev. 4
44
Freescale Semiconductor
Share Link: 