MPC5200CVR466BR2 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
MPC5200CVR466BR2 Datasheet PDF : 72 Pages
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SCK
( CLKPOL = 0 )
Output
SCK
( CLKPOL = 1 )
Output
SS
Output
1
11
10
2
2
10
11
3
8
9
4
5
MOSI
Output
6
6
MISO
Input
7
7
Figure 32. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0)
Table 37. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)
Sym
Description
Min
Max
Units
1
Cycle time
4
1024
IP-Bus Cycle(1)
2
Clock high or low time
2
512
IP-Bus Cycle(1)
3
Slave select to clock delay
15.0
—
ns
4
Output Data valid after Slave Select (SS)
—
50.0
ns
5
Output Data valid after SCK
—
50.0
ns
6
Input Data setup time
50.0
—
ns
7
Input Data hold time
0.0
—
ns
8
Slave disable lag time
15.0
—
ns
9
Sequential Transfer delay
1
—
IP-Bus Cycle(1)
1 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
SpecID
A11.12
A11.13
A11.14
A11.15
A11.16
A11.17
A11.18
A11.19
A11.20
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5200B Data Sheet, Rev. 4
42
Freescale Semiconductor
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