PSB 2120
Figure 2
DC/DC-Conversion
The PSB 2120 contains a SIPMOS-transistor for power handling. Non-isolated and isolated SMPS-
configurations are possible. Logic and analog circuits are implemented in CMOS in order to achieve
low power dissipation.
The error amplifier compares the sensed voltage with a reference attached to VP and thus controls
the Pulse Width Modulator (PWM). The conversion frequency is generated by a sawtooth oscillator
which can be controlled by external RC-components (figure 4) or by an external synchronization
signal. The PSB 2120 is synchronized by the rising edge of the sync signal, whose frequency must
be 10 % higher than the free run frequency, determined by the RC-components. The SYNC-pin can
also be used as a trigger-output. As long as the capacitor of the sawtooth oscillator is discharged,
SYNC is high.
The output of the PWM is processed by the control logic and fed to the SIPMOS-transistor. The
control logic suppresses higher oscillations of the regulation loop caused e.g. in case of current limit
detection.
Semiconductor Group
7