PSD813F1AV-90J View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

PSD813F1AV-90J

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 3.3V

STMicroelectronics 

PSD813F1V

Table 72. ISC Timing (3V devices)

Symbol

Parameter

Conditions

tISCCF

Clock (TCK, PC1) Frequency (except for

PLD)

tISCCH Clock (TCK, PC1) High Time (except for PLD)

tISCCL Clock (TCK, PC1) Low Time (except for PLD)

tISCCFP Clock (TCK, PC1) Frequency (PLD only)

tISCCHP Clock (TCK, PC1) High Time (PLD only)

tISCCLP Clock (TCK, PC1) Low Time (PLD only)

tISCPSU ISC Port Set Up Time

tISCPH ISC Port Hold Up Time

tISCPCO ISC Port Clock to Output

tISCPZV ISC Port High-Impedance to Valid Output

tISCPVZ

ISC Port Valid Output to

High-Impedance

Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.

2. For Program or Erase PLD only.

(Note 1)

(Note 1)

(Note 1)

(Note 2)

(Note 2)

(Note 2)

-15

Min Max

-20

Unit

Min Max

10

9 MHz

45

51

ns

45

51

ns

2

2 MHz

240

240

ns

240

240

ns

13

15

ns

10

10

ns

36

40 ns

36

40 ns

36

40 ns

Table 73. Power-down Timing (5V devices)

Symbol

Parameter

Conditions

tLVDV

ALE Access Time from Power-down

tCLWH

Maximum Delay from

APD Enable to Internal PDN Valid

Signal

Note: 1. tCLCL is the period of CLKIN (PD1).

Using CLKIN

(PD1)

-90

-12

-15

Unit

Min Max Min Max Min Max

90

120

150 ns

15 * tCLCL1

µs

Table 74. Power-down Timing (3V devices)

Symbol

Parameter

Conditions

tLVDV

ALE Access Time from Power-down

tCLWH

Maximum Delay from APD Enable to

Internal PDN Valid Signal

Note: 1. tCLCL is the period of CLKIN (PD1).

Using CLKIN

(PD1)

-15

Min Max

150

-20

Unit

Min Max

200 ns

15 * tCLCL1

µs

99/110

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