CS4630
knowledge, Special Cycles, and Dual Address Cy-
cle transactions are not generated.
The PCI bus transactions supported by the CS4630
device are summarized in Table 1. Note that no
Target Abort conditions are signalled by the de-
vice. Byte, Word, and Doubleword transfers are
supported for Configuration Space accesses. Only
Doubleword transfers are supported for Register or
Memory area accesses. Bursting is not supported
for host-initiated transfers to/from the CS4630 in-
ternal register space, RAM memory space, or PCI
configuration space (disconnect after first phase of
transaction is completed).
Initiator
Host
Host
Host
Host
Host
Host
Host
Host
CS46XX
CS46XX
CS46XX
CS46XX
Target
Registers (BA0)
Registers (BA0)
Memories (BA1)
Memories (BA1)
Config Space 1
Config Space 1
Legacy H/W
Legacy H/W
Host System
Host System
South Bridge
South Bridge
Type
Mem Write
Mem Read
Mem Write
Mem Read
Config Write
Config Read
I/O Write
I/O Read
Mem Write
Mem Read
I/O Write
I/O Read
PCI Dir
In
Out
In
Out
In
Out
In
Out
Out
In
Out
In
Table 1. PCI Interface Transaction Summary
16
DS445PP1