ISPLSI3256E-100LQ View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
MFG CO.
ISPLSI3256E-100LQ Datasheet PDF : 15 Pages
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Specifications ispLSI 3256E
Pin Description
Pin Name
I/O
Description
Input/Output pins – These are the general purpose I/O pins used by the logic array.
GOE0, GOE1
Global Output Enable input pins.
TOE
RESET
Test Output Enable pin – This pin tristates all I/O pins when a logic low is driven.
Active Low (0) Reset pin – Resets all of the GLB and I/O registers in the device.
Y0, Y1, Y2
Y3, Y4
BSCAN/ispEN
TDI/SDI
TCK/SCLK
TMS/MODE
TRST/NC1
TDO/SDO
Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on
the device.
Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the I/O cells
on the device.
Input – Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP
controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP State
Machine control pins MODE, SDI, SDO and SCLK are enabled. High-to-low transition of this pin will put
the device in the programming mode and put all I/O pins in the high-Z state.
Input – This pin performs two functions. It is the Test Data input pin when ispEN is logic high. When
ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also
used as one of the two control pins for the ISP State Machine.
Input – This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When
ispEN is logic low, it functions as a clock pin for the Serial Shift Register.
Input – This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high.
When ispEN is logic low, it functions as a pin to control the operation of the ISP State Machine.
Input – Test Reset, active low to reset the Boundary Scan State Machine.
Output – This pin performs two functions. When ispEN is logic low, it functions as the pin to read the
ISP data. When ispEN is high, it functions as Test Data Out.
GND
Ground (GND)
VCC
NC1
Vcc
No Connect.
1. NC pins are not to be connected to any active signals, VCC or GND.
Pin Locations
Signal
GOE0, GOE1
TOE
RESET
Y0, Y1, Y2, Y3, Y4
ispEN/BSCAN
SDI/TDI
SCLK/TCK
MODE/TMS
TRST/NC1
SDO/TDO
GND
VCC
NC1
304-Pin PQFP
195, 185
215
53
43, 33, 205, 175, 165
63
23
73
13
225
155
9, 19, 39, 49, 69, 85, 95, 115, 125, 145, 161, 171,
191, 201, 221, 237, 247, 267, 277, 297
1, 29, 59, 77, 105, 135, 153, 181, 211, 229, 257,
287, 304
320-Ball BGA
AD11, AC14
AC6
A17
A14, B11, AD8, AB16, AA18
B19
C9
D20
D7
AA5
AB21
D6, C8, B13, A16, D19, F21, H22, N23, T24, W21,
AA19, AB17, AC12, AD9, AA6, W4, U3, M2, J1, F4
D4, B10, B18, D21, K23, V23, AA21, AC15, AC7,
AA4, R2, G2, C3
A1, A2, A23, A24, B1, B2, B23, B24, AC1, AC2,
AC23, AC24, AD1, AD2, AD23, AD24
1. NC pins are not to be connected to any active signals, VCC or GND.
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