IDT7027S(2018) View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
IDT7027S Datasheet PDF : 20 Pages
| |||
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1,3)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
CE"B"
BUSY"B"
tAPS (2)
tBAC
tBDC
3199 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1)
ADDR"A"
ADDR"B"
BUSY"B"
tAPS (2)
ADDRESS "N"
MATCHING ADDRESS "N"
tBAA
tBDA
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Chip Enable Truth Table.
3199 drw 14
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
7027X15
Com'l Only
7027X20
Com'l
& Ind
7027X25
Com'l
& Ind
Symbol
Parameter
Min. Max. Min. Max. Min. Max.
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
tWR
Write Recovery Time
0
____
0
____
0
____
tINS
Interrupt Set Time
____
15
____
20
____
20
tINR
Interrupt Reset Time
____
15
____
20
____
20
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
7027X35
Com'l Only
Min. Max.
0
____
0
____
____
25
____
25
7027X55
Com'l Only
Min. Max. Unit
0
____
ns
0
____
ns
____
40
ns
____
40
ns
3199 tbl 15
61.442
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