IDT7007L55J(1999) View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
IDT7007L55J Datasheet PDF : 21 Pages
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IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
7007X15
Com'l Only
7007X20
Com'l Only
7007X25
Com'l &
Military
Symbol
BUSY TIMING (M/S=VIH)
Parameter
Min. Max. Min. Max. Min. Max. Unit
tBAA
BUSY Access Time from Address Match
____
15
____
20
____
20
ns
tBDA
BUSY Disable Time from Address Not Matched
____
15
____
20
____
20
ns
tBAC
BUSY Access Time from Chip Enable Low
____
15
____
20
____
20
ns
tBDC
BUSY Access Time from Chip Enable High
____
15
____
17
____
17
ns
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
18
____
30
____
30
ns
tWH
Write Hold After BUSY(5)
BUSY TIMING (M/S=VIL)
12
____
15
____
17
____
ns
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
0
____
12
____
0
____
15
____
0
____
ns
17
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
30
____
45
____
50
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
25
____
30
____
35
ns
2940 tbl 14a
7007X35
Com'l &
Military
7007X55
Com'l, Ind
& Military
Symbol
BUSY TIMING (M/S=VIH)
Parameter
Min. Max. Min. Max. Unit
tBAA
BUSY Access Time from Address Match
____
20
____
45
ns
tBDA
BUSY Disable Time from Address Not Matched
____
20
____
40
ns
tBAC
BUSY Access Time from Chip Enable Low
____
20
____
40
ns
tBDC
BUSY Access Time from Chip Enable High
____
20
____
35
ns
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
35
____
40
ns
tWH
Write Hold After BUSY(5)
BUSY TIMING (M/S=VIL)
25
____
25
____
ns
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
0
____
0
____
ns
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
60
____
80
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
45
____
65
ns
NOTES:
2940 tbl 14b
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD tWP (actual) or tDDD tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
13
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