THEORY OF OPERATION
The AD831 consists of a mixer core, a limiting amplifier, a low
noise output amplifier, and a bias circuit (Figure 1).
The mixer’s RF input is converted into differential currents by
a highly linear, Class A voltage-to-current converter, formed by
transistors Q1, Q2 and resistors R1, R2. The resulting currents
drive the differential pairs Q3, Q4 and Q5, Q6. The LO input is
through a high gain, low noise limiting amplifier that converts the
–10 dBm LO input into a square wave. This square wave drives
the differential pairs Q3, Q4 and Q5, Q6 and produces a high
level output at IFP and IFN—consisting of the sum and differ-
ence frequencies of the RF and LO inputs—and a series of lower
level outputs caused by odd harmonics of the LO frequency mix-
ing with the RF input.
An on-chip network supplies the bias current to the RF and LO
inputs when these are ac-coupled; this network is disabled when
the AD831 is dc-coupled.
AD831
When the integral output amplifier is used, pins IFN and IFP
are connected directly to pins AFN and AFP; the on-chip load
resistors convert the output current into a voltage that drives
the output amplifier. The ratio of these load resistors to resistors
R1, R2 provides nominal unity gain (0 dB) from RF-to-IF. The
expression for the gain, in decibels, is
GdB
= 20
log10
Ê
ËÁ
4
p
ˆ
¯˜
Ê
ËÁ
1
2
ˆ
¯˜
Ê
ËÁ
p
2
ˆ
¯˜
(1)
where:
4 is the amplitude of the fundamental component of a
p squarewave.
1 is the conversion loss.
2
p is the small signal dc gain of the AD831 when the LO input
2 is driven fully positive or negative.
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Figure 1. Simplified Schematic Diagram
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REV. C
–7–