KSZ8051MNL View Datasheet(PDF) - Micrel
Part Name
Description
MFG CO.
KSZ8051MNL Datasheet PDF : 59 Pages
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Micrel, Inc.
KSZ8051MNL/RNL
Strapping Options – KSZ8051RNL
Pin Number
15
14
13
Pin Name
PHYAD2
PHYAD1
PHYAD0
18
CONFIG2
29
CONFIG1
28
CONFIG0
Type(1)
Ipd/O
Ipd/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Pin Function
The PHY Address is latched at de-assertion of reset and is configurable to any value
from 0 to 7.
The default PHY Address is 00001.
PHY Address 00000 is enabled only if the B-CAST_OFF strapping pin is pulled high.
PHY Address bits [4:3] are set to ‘00’ by default.
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0]
Mode
001
RMII
101
000, 010 – 100, 110, 111
RMII Back-to-Back
Reserved – not used
20
ISO
Ipd/O ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into register 0h bit 10.
31
SPEED
Ipu/O SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
At the de-assertion of reset, this pin value is latched into register 0h bit 13 as the
Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement)
as the Speed capability support.
16
DUPLEX
Ipu/O DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
At the de-assertion of reset, this pin value is latched into register 0h bit 8.
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
At the de-assertion of reset, this pin value is latched into register 0h bit 12.
19
B-CAST_OFF
Ipd/O
Broadcast Off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
21
NAND_Tree# Ipu/Opu NAND Tree Mode
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Note:
1. Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin with internal pull-up (see Electrical
Characteristics for value) otherwise.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset,
and consequently cause the PHY strap-in pins on the RMII signals to be latched to the unintended high/low states. In this case, external pull-ups (4.7K)
or pull-downs (1.0K) should be added on these PHY strap-in pins to ensure the intended values are strapped-in correctly.
July 2010
18
M9999-070910-1.0
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