Function Table
Inputs
Outputs
Clear
Clock
D
Q
Q(1)
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q0
Q0
H = HIGH Level (steady state) L = LOW Level (steady state)
X = Don't Care
↑ = Transition from LOW-to-HIGH Level
Q0 = the level of Q before the indicated steady-state input conditions were established.
Note:
1. Applies to DM74ALS175 only.
Logic Diagrams
DM74ALS174
DM74ALS175
©1986 Fairchild Semiconductor Corporation
DM74ALS174, DM74ALS175 Rev. 1.2
3
www.fairchildsemi.com