PD_VCC
10k
PLL_LOCK
PD_VEE
All on-chip resistors have ±20% tolerance at room temperature.
Fig. 7 PLL_LOCK Output Circuit
PD_VCC
10k
IJI
5k
VCC
30k
A
PD_VEE
Fig. 8 IJI Output Circuit
SDO
SDO
+
-
CD_VEE RSET
Fig. 9 SDO/SDO Output Circuit
10k
D0 - D19,
SYNC_DETECT_DISABLE
VCC3
2k
BIAS
VEE3
Fig. 10 Data Input and SYNC_DETECT_DISABLE Circuit
5k
PCLK_IN
VCC
1k
BIAS
VEE
Fig. 11 PCLK_IN Circuit
10k
RESET
VCC
20k
BIAS
VEE
Fig. 12 RESET Circuit
8
GENNUM CORPORATION
522 - 26 - 00