WAVEFORM 8 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
M74HC690
tPLZ, tPZL
The 1KΩ load resistors should be connected
between outputs and VCC line and the 50pF load
capacitor should be connected between outputs
and GND line.
All inputs except G input should be connected to
VCC or GND line such that outputs will be in low
logic level while G input is held low.
tPHZ, tPZH
The 1KΩ load resistors and the 50pF load
capacitors should be connected between each
output and GND line.
All inputs except G input should be connected to
VCC or GND line such that outputs will be in low
logic level while G input is held low.
WAVEFORM 9 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
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