R480CPAA View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

MFG CO.

R480CPAA

Lightwave Receiver with CML Data Output for up to 2.488 Gbits/s Applications

Agere -> LSI Corporation 

R480-Type Lightwave Receiver with CML Data Output

for up to 2.488 Gbits/s Applications

Data Sheet, Rev. 1

September 2001

PWB Layout Guidelines

s The data outputs are designed to drive 50 Ω loads.

s Data output traces must be controlled-impedance lines and the termination impedance must match the line

impedance. Avoid 90° bends in the traces. Paired lines (i.e., DATA and DATA) must be equal in length.

s Data output lines should be as short and straight as possible and should be shielded from noise sources to pre-

vent noise from feeding back into the receiver.

s Use high-quality multilayer printed-wiring boards. A ground plane should occupy the area directly beneath the

receiver.

4, 7, 9, 12,

14—17, 19, 20

8, 22

VCC

0.1 µF

NOTE 2

3 LOS (FLAG)

DATA 10

DATA 11

OILV

23

1 µH

+

2.2 µF

+5 V

15 µF

50 Ω TRANSMISSION

LINE (2X)

0.1 µF

NOTE 1

50 Ω

1-934(C)d

Note 1: Data outputs must be ac-coupled on customer board. Use a 0.1 µF chip capacitor with a low ESR. For optimum receiver performance,

both data outputs must be terminated in equivalent loads, even if one of the outputs is not being used.

Note 2: The 0.1 µF VCC power supply bypass capacitors should be high-quality, low ESR chip capacitors that are located as close as possible to

the appropriate power supply leads and should provide a low-inductance path to the ground plane.

Figure 1. Biasing and Interfacing to the R480-Type 2.5 Gbits/s Receiver

6

Agere Systems Inc.

Share Link: