MCP2030-ISL View Datasheet(PDF) - Microchip Technology

Part Name

Description

MFG CO.

MCP2030-ISL

Three-Channel Analog Front-End Device

Microchip Technology 

MCP2030

AC Characteristics (Continued)

Electrical Specifications: Standard Operating Conditions (unless otherwise stated)

Supply Voltage

Operating temperature

LCCOM connected to VSS

LC Signal Input

Carrier Frequency

2.0V ≤ VDD ≤ 3.6V

-40°C ≤ TA ≤ +85°C

Sinusoidal 300 mVPP

125 kHz

LCCOM connected to VSS

Parameters

Demodulator Discharge Time (delay time

of demodulated output to fall)

Sym.

TDF

Min.

—

Typ†

50

Max.

—

Rise time of LFDATA

Fall time of LFDATA

TRLFDATA

—

0.5

—

TFLFDATA

—

0.5

—

AGC stabilization time

(TAGC + TPAGC)

AGC initialization time

High time after AGC initialization time

Gap time after AGC stabilization time

Time element of pulse

Time from exiting Sleep or POR to being

ready to receive signal

Minimum time AGC level must be held

after receiving AGC Preserve command

Internal RC oscillator frequency

Inactivity timer time-out

Alarm timer time-out

LC Pin Input Resistance for

LCX, LCY, LCZ pins

LC Pin Input Parasitic Capacitance for

LCX, LCY, LCZ pins

Minimum output enable filter high time

OEH (Bits Config0<8:7>)

01 = 1 ms

10 = 2 ms

11 = 4 ms

00 = Filter Disabled

Minimum output enable filter low time

OEL (Bits Config0<6:5>)

00 = 1 ms

01 = 1 ms

10 = 2 ms

11 = 4 ms

Maximum output enable filter period

TSTAB

4

—

TAGC

TPAGC

TGAP

TE

TRDY

—

3.5

—

62.5

200

—

100

—

—

—

TPRES

5*

—

FOSC

TINACT

TALARM

RIN

CIN

TOEH

27

13.5

27

—

—

32

16

32

800*

24*

TOEL

32 (~1 ms) —

64 (~2 ms) —

128 (~4 ms) —

—

—

32 (~1 ms) —

32 (~1 ms) —

64 (~2 ms) —

128 (~4 ms) —

TOET

—

—

—

—

—

50*

—

35.5

17.75

35.5

—

—

—

—

—

—

—

—

—

—

Units

μs

μs

μs

ms

Conditions

VDD = 3.0V

MOD depth setting = 33%

Input conditions:

Amplitude = 300 mVPP

Modulation depth = 100%

VDD = 3.0V. Time is measured from 10% to

90% of amplitude

VDD = 3.0V

Time is measured from 10% to 90% of

amplitude

ms

μs

μs

μs Minimum pulse width

ms

ms

kHz

ms

ms

kΩ

pF

clock

count

AGC level must not change more than 10%

during TPRES.

Internal clock trimmed at 32 kHz during test

512 cycles of RC oscillator @ FOSC

1024 cycles of RC oscillator @ FOSC

LCCOM grounded, VDD = 3V,

FCARRIER = 125 kHz.

LCCOM grounded, VDD = 3V,

FCARRIER = 125 kHz.

RC oscillator = FOSC (see FOSC specification

for variations).

Viewed from the pin input:

(Note 1)

clock

count

RC oscillator = FOSC

Viewed from the pin input:

(Note 2)

RC oscillator = FOSC

OEH

01

01

01

01

10

10

10

10

11

11

11

11

00

Note

OEL TOEH

00 = 1 ms

01 = 1 ms

10 = 1 ms

11 = 1 ms

TOEL

1 ms (Filter 1)

1 ms (Filter 1)

2 ms (Filter 2)

4 ms (Filter 3)

—

— 96 (~3 ms)

—

— 96 (~3 ms)

—

— 128 (~4 ms)

—

— 192 (~6 ms)

00 = 2 ms

01 = 2 ms

10 = 2 ms

11 = 2 ms

1 ms (Filter 4)

1 ms (Filter 4)

2 ms (Filter 5)

4 ms (Filter 6)

—

— 128 (~4 ms)

—

— 128 (~4 ms) clock

—

— 160 (~5 ms) count

—

— 250 (~8 ms)

00 = 4 ms

01 = 4 ms

10 = 4 ms

11 = 4 ms

1 ms (Filter 7)

1 ms (Filter 7)

2 ms (Filter 8)

4 ms (Filter 9)

—

— 192 (~6 ms)

—

— 192 (~6 ms)

—

— 256 (~8 ms)

—

— 320 (~10 ms)

XX = Filter Disabled

—

—

—

LFDATA output appears as long as input

signal level is greater than VSENSE.

* Parameter is characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

1: Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF).

2: Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).

© 2005 Microchip Technology Inc.

DS21981A-page 5

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