MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Timing Diagrams (Note 31)
Read Cycle
VIH
RAS
VIL
VIH
LCAS/UCAS
VIL
VIH
A0~A8
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRC
tRAS
tCRP
tRCD
tCSH
tRSH
tCAS
tASR
tRAH
tRAD
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tRAL
tCAL
tRCS
tRP
tRPC
tCRP
tASR
ROW
ADDRESS
tRRH
tRCH
Hi-Z
tDZC
tCDD
tCAC
tAA
tCLZ
tRAC
tDZO
tOEA
tOEA
Hi-Z
tREZ
tOHR
tWEZ
tOFF
tOHC
DATA VALID
tOCH
tOEZ
tODD
Hi-Z
tORH
Note 31
Indicates the don't care input.
VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max)
Indicates the invalid output.
8
M5M4V4265CJ,TP-5,-5S:under development