GS9020-CTV View Datasheet(PDF) - Gennum -> Semtech
Part Name
Description
MFG CO.
GS9020-CTV Datasheet PDF : 30 Pages
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AC ELECTRICAL CHARCTERISTICS
VDD = 5.0 V, TA = 0 - 70°C unless otherwise shown.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
TEST
LEVEL
Serial Input Clock
ƒSCI
Frequency
-
-
540
MHz
Serial Data Input
tSS
Setup Time
600
-
-
ps
1
Serial Data Input Hold
tSH
Time
600
-
-
ps
1
Serial Data Output
Duty Cycle Distortion
-
5
-
%
Serial Output Jitter
540Mb/s at eye crossing
-
360
-
ps p-p
Serial Data Output
Rise Time
-
600
-
ps
Parallel Clock Output
Jitter
27MHz at 50% voltage
level
-
700
-
ps p-p
Input Timing
t1
20
-
-
ns
2
t2
-
-
9
ns
2
Output Delay Time
tOD
with 25pF loading
T/2
-
T/2+7
ns
3
Output Hold Time
tOH
with 25pF loading
T/2-3
-
-
ns
3
Output Setup Time
tOS
with 25pF loading
T/2-7
-
-
ns
3
Flag Port Disable Time
tFDIS
with 25pF loading
-
-
T/2+0.5
ns
Flag Port Enable Time
tFEN
with 25pF loading
-
-
T/2+1
ns
I²C Clock Frequency
ƒSCL
-
-
400
kHz
Host Interface Setup
tHS
Time
6
-
-
ns
4
Host Interface Hold
tHH
Time
6
-
-
ns
4
Host Interface Output
Enable Time
tHEN
with 25pF loading
-
-
21
ns
4
Host Interface Output
Disable Time
tHDIS
with 25pF loading
-
-
10
ns
4
Reset Time Pulse
Width
tRESET
100
-
-
ns
NOTES
1. The serial clock rising edge should occur at the centre of the data period for optimum performance. (See Figure 1)
2. Since the GS9020 does not have a parallel clock input, it is not possible to define timing details relative to it. Instead the GS9020 has
a parallel clock output and all timing information is relative to PCLKOUT. The flag port pins (FL[4:0], F_R/W, S[1:0]) are the only
inputs where the timing details are important. The timing requirements are shown in Figure 2.
3. These times are relative to the rising edge of PCLKOUT as shown in Figure 3. Note that the data transitions at the falling edge of
PCLKOUT. T is the parallel clock period in ns.
4. The Host Interface signals, P[7:0], R/W, A/D and CS are asynchronous to the parallel clock.
3
521 - 66 - 05
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