CY7C168A-15PC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
CY7C168A-15PC Datasheet PDF : 10 Pages
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CY7C168A
Switching Characteristics Over the Operating Range[2,6]
7C168A-15 7C168A-20 7C168A-25 7C168A-35 7C168A-45
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
15
20
25
35
45
ns
tAA
Address to Data Valid
15
20
25
35
45 ns
tOHA
Output Hold from Address Change 5
5
5
5
5
ns
tACE
tLZCE
tHZCE
Power Supply Current
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8]
15
20
25
35
45 ns
5
5
5
5
5
ns
8
8
10
15
15 ns
tPU
CE LOW to Power Up
0
0
0
0
0
ns
tPD
CE HIGH to Power-Down
15
20
20
20
25 ns
tRCS
Read Command Set-Up
0
0
0
0
0
ns
tRCH
Read Command Hold
WRITE CYCLE[9]
0
0
0
0
0
ns
tWC
Write Cycle Time
15
20
20
25
40
ns
tSCE
CE LOW to Write End
12
15
20
25
30
ns
tAW
Address Set-Up to Write End
12
15
20
25
30
ns
tHA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tPWE
WE Pulse Width
12
15
15
20
20
ns
tSD
Data Set-Up to Write End
10
10
10
15
15
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
7
7
7
5
5
ns
tHZWE
WE LOW to High Z[7, 8]
5
5
5
5
10
ns
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
C168A-5
Notes:
6. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZ is less than tLZ for all devices. Transition is measured ±500 mV from steady state voltage with specified loading in part
(b) of AC Test Loads and Waveforms.
8. tHZCE and tHZWE are tested with CL = 5 pF as in part (a) of Test Loads and Waveforms. Transition is measured ±500 mV from steady state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signal must be LOW to initiate a write and either signal can terminate a
write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE = VIL.
Document #: 38-05029 Rev. **
Page 4 of 10
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