AS4LC4M4883C View Datasheet(PDF) - Austin Semiconductor
Part Name
Description
MFG CO.
AS4LC4M4883C Datasheet PDF : 20 Pages
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AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP
tRP
RAS
V
V
IH
IL
tCSH
tPC
tRSH
tCRP
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tCP
CAS
V
V
IH
IL
,, ,,,, ,,, , , , , ADDR
V IH
V IL
,,,,,, ,,, ,,, ,,,,, , WE
V IH
V IL
,,,,,,,,,,,,,,,,,,,,,,,, ,,,, DQ
V
V
IOH
IOL
, ,,,,,, OE
V IH
V IL
tASR
tRAD
tRAH
tAR
tASC
tACH
tCAH
ROW
tWRP tWRH
COLUMN
tWCS
tCWL
tWCH
tWP
NOTE 1
tWCR
tDHR
tDS
tDH
VALID DATA
tASC
tACH
tCAH
COLUMN
tWCS
tCWL
tWCH
tWP
tDS
tDH
VALID DATA
tASC
tACH
tRAL
tCAH
COLUMN
tWCS
tCWL
tWCH
tWP
tRWL
tDS
tDH
VALID DATA
ROW
DON’T CARE
UNDEFINED
NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
SYM
tACH
tAR
tASC
tASR
tCAH
tCAS
tCP
tCRP
tCSH
tCWL
tDH
tDHR
tDS
tPC
-6
MIN MAX
15
45
0
0
10
12 10,000
10
5
50
15
10
40
0
30
-7
MIN MAX
15
55
0
0
12
15 10,000
10
5
55
15
12
50
0
35
-8
MIN MAX
20
60
0
0
15
20 10,000
10
5
60
20
15
55
0
40
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
tRAD
tRAH
tRAL
tRASP
tRCD
tRP
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
tWRH
tWRP
-6
MIN MAX
15 30
10
30
60 100,000
16 45
40
13
15
10
40
0
10
10
10
-7
MIN MAX
15 35
10
35
70 100,000
16 50
50
15
15
12
50
0
12
10
10
-8
MIN MAX
15 40
10
40
80 100,00
20 60
60
15
20
15
60
0
15
10
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS4LC4M4
Rev. 11/97
DS000022
2-85
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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