ADUC814BRU View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
ADUC814BRU Datasheet PDF : 72 Pages
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ADuC814
Pin No. Mnemonic Type Function
17
CREF
I
Decoupling Input for On-Chip Reference. Connect 0.1 µF between this pin and AGND.
18–21 P1.4–P1.7
I
Port 1.4 to P1.7. These pins have no digital output drivers, i.e., they can only function as digital inputs,
for which 0 must be written to the port bit. These port pins also have the following analog functionality:
18
P1.4/ADC2 I
ADC Input Channel 2. Selected via ADCCON2 SFR.
19
P1.5/ADC3 I
ADC Input Channel 2. Selected via ADCCON2 SFR.
20
P1.6/ADC4/ I/O
ADC Input Channel 4. Selected via ADCCON2 SFR. The voltage DAC Channel 0 can also be configured
DAC0
to appear on P1.6.
21
P1.7/
I/O
ADC Input Channel 5, selected via ADCCON2 SFR. The voltage DAC Channel 1 can also be configured
ADC5/DAC1
to appear on P1.7.
22–24 P3.5–P3.7
I/O
Bidirectional Port Pins with Internal Pull-Up Resistors. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs
,with Port 3 pins being pulled low externally, they source current because of the internal pull-up
resistors. When driving a 0-to-1 output transition a strong pull-up is active during S1 of the instruction
cycle. Port 3 pins also have various secondary functions which are described as follows.
22
P3.5/T1
I/O Timer/Counter 1 Input. P3.5–P3.7 pins also have SPI interface functions. To enable these functions,
Bit 0 of the CFG814 SFR must be set to 1.
22
P3.5/SS
I/O
This pin also functions as the Slave Select input for the SPI interface when the device is operated in
/EXTCLK
slave mode. P3.5 can also function as an input for an external clock. This clock effectively bypasses the
PLL. This function is enabled by setting Bit 1 of the CFG814 SFR.
23
P3.6/MISO
I/O
SPI Master Input/Slave Output Data Input/Output Pin.
24
P3.7/SDATA/ I/O
SPI Master Output/Slave Input Data Input/Output Pin.
MOSI
25
SCLOCK
I/O
Serial Clock Pin for SPI Serial Interface Clock.
26
XTAL1
I
Input to the Crystal Oscillator Inverter.
27
XTAL2
O
Output from the Crystal Oscillator Inverter.
28
DVDD
S
Analog Positive Supply Voltage, 3 V or 5 V.
I = Input, O = Output, S = Supply, G - Ground.
The following notes apply to the entire data sheet:
• In bit designation tables, set implies a Logic 1 state, and cleared implies a Logic 0 state, unless otherwise stated.
• Set and cleared also imply that the bit is set or cleared by the ADuC814 hardware, unless otherwise stated.
• User software should not write to reserved or unimplemented bits as they may be used in future products.
Rev. A | Page 11 of 72
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