ADMC331BST View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

ADMC331BST

Single Chip DSP Motor Controller

Analog Devices 

ADMC331

Program memory can store both instructions and data, permit-

ting the ADMC331 to fetch two operands in a single cycle—

one from program memory and one from data memory. The

ADMC331 can fetch an operand from on-chip program memory

and the next instruction in the same cycle.

The ADMC331 writes data from its 16-bit registers to the 24-bit

program memory using the PX register to provide the lower

eight bits. When it reads data (not instructions) from 24-bit

program memory to a 16-bit data register, the lower eight bits

are placed in the PX register.

The ADMC331 can respond to a number of distinct DSP core

and peripheral interrupts. The DSP core interrupts include

serial port receive and transmit interrupts, timer interrupts,

software interrupts and external interrupts. The motor control

peripherals also produce interrupts to the DSP core.

The two serial ports (SPORTs) provide a complete synchronous

serial interface with optional companding in hardware and a

wide variety of framed and unframed data transmit and receive

modes of operation. Each SPORT can generate an internal

programmable serial clock or accept an external serial clock.

Boot loading of both the program and data memory RAM of the

ADMC331 is through the serial port SPORT1.

A programmable interval counter is also included in the DSP

core and can be used to generate periodic interrupts. A 16-bit

count register (TCOUNT) is decremented every n processor

cycle, where n–1 is a scaling value stored in the 8-bit TSCALE

register. When the value of the counter reaches zero, an interrupt is

generated and the count register is reloaded from a 16-bit pe-

riod register (TPERIOD).

The ADMC331 instruction set provides flexible data moves and

multifunction (one or two data moves with a computation) instruc-

tions. Each instruction is executed in a single 38.5 ns processor

cycle (for a 13 MHz CLKIN). The ADMC331 assembly lan-

guage uses an algebraic syntax for ease of coding and readabil-

ity. A comprehensive set of development tools support program

development. For further information on the DSP core, refer to

the ADSP-2100 Family User’s Manual, Third Edition, with par-

ticular reference to the ADSP-2171.

Serial Ports

The ADMC331 incorporates two complete synchronous serial

ports (SPORT0 and SPORT1) for serial communication and

multiprocessor communication. Following is a brief list of capa-

bilities of the ADMC331 SPORTs. Refer to the ADSP-2100

Family User’s Manual, Third Edition, for further details.

• SPORTs are bidirectional and have a separate, double-buffered

transmit and receive section.

• SPORTs can use an external serial clock or generate their

own serial clock internally.

• SPORTs have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated. Frame

synchronization signals are active high or inverted, with either of

two pulsewidths and timings.

• SPORTs support serial data word lengths from 3 bits to 16

bits and provide optional A-law and µ-law companding ac-

cording to ITU (formerly CCITT) recommendation G.711.

• SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An interrupt

is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive

and transmit a 24-word or 32-word, time-division multi-

plexed, serial bitstream.

• SPORT1 can be configured to have two external interrupts

(IRQ0 and IRQ1), and the Flag In and Flag Out signals. The

internally generated serial clock may still be used in this con-

figuration.

• SPORT1 is the default input for program and data memory

boot loading. The RFS1 pin can be configured internal to the

ADMC331 as an SROM/E2PROM reset signal.

• SPORT1 has two data receive pins (DR1A and DR1B). The

DR1A pin is intended for synchronous boot loading from the

external SROM/E2PROM. The DR1B pin can be used as the

data receive pin for boot loading from an external asynchro-

nous (UART) connection (SCI compatible), an external

synchronous connection as the data receive pin for an external

device communicating over the debugger interface, or as the

data receive pin for a general purpose SPORT after booting.

These two pins are internally multiplexed onto the one DR1

port of the SPORT. The particular data receive pin selected is

determined by a bit in the MODECTRL register.

REV. B

–9–

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