ADMC331BST View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

ADMC331BST

Single Chip DSP Motor Controller

Analog Devices 

ADMC331

TIMING PARAMETERS

Parameter

Min

Max Unit

Clock Signals

tCK is defined as 0.5 tCKI. The ADMC331 uses an input clock with a frequency equal

to half the instruction rate; a 13 MHz input clock (which is equivalent to 76.9 ns)

yields a 38.5 ns processor cycle (equivalent to 26 MHz). tCK values within the range

of 0.5 tCKI period should be substituted for all relevant timing parameters to obtain

specification value.

Example: tCKH = 0.5 tCK – 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns.

Timing Requirements:

tCKI

CLKIN Period

tCKIL

CLKIN Width Low

tCKIH

CLKIN Width High

Switching Characteristics:

tCKL

CLKOUT Width Low

tCKH

CLKOUT Width High

tCKOH

CLKIN High to CLKOUT High

Control Signals

Timing Requirement:

tRSP

RESET Width Low

PWM Shutdown Signals

Timing Requirement:

tPWMTPW

PWMTRIP Width Low

76.9

150

ns

20

ns

20

ns

0.5 tCK – 10

ns

0.5 tCK – 10

ns

0

20

ns

5 tCK1

ns

2 tCK

ns

NOTE

1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

CLKIN

CLKOUT

tCKI

tCKIH

tCKIL

tCKOH

tCKH

tCKL

Figure 1. Clock Signals

REV. B

–3–

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