AD7937AR View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7937AR Datasheet PDF : 8 Pages
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AD7937
PIN FUNCTION DESCRIPTIONS
Pin
1
2
3
4
5
6–11
13, 14
12
15
16
17
Mnemonic
AGNDA
IOUTA
RFBA
VREFA
CS
DB0–DB7
DGND
A0
A1
CLR
18
WR
19
UPD
20
VDD
21
VREFB
22
RFBB
23
IOUTB
24
AGNDB
Description
Analog Ground for DAC A.
Current output terminal of DAC A.
Feedback resistor for DAC A.
Reference input to DAC A.
Chip Select Input Active low.
Eight data inputs, DB0–DB7.
Digital Ground.
Address Line 0.
Address Line 1.
Clear Input. Active low. Clears all
registers.
Write Input. Active low.
Updates DAC Registers from inputs
registers.
Power supply input. Nominally 5 V to
15 V, with ± 10% tolerance.
Reference input to DAC B.
Feedback resistor for DAC B.
Current output terminal of DAC B.
Analog Ground for DAC B.
PIN CONFIGURATION
SOIC
AGNDA 1
24 AGNDB
IOUTA 2
23 IOUTB
RFBA 3
22 RFBB
VREFA
CS
DB0
DB1
4
21 VREFB
5 AD7937 20 VDD
6 TOP VIEW 19 UPD
7 (Not to Scale) 18 WR
DB2 8
17 CLR
DB3 9
16 A1
DB4 10
15 A0
DB5 11
14 DB7
DGND 12
13 DB6
CIRCUIT INFORMATION – D/A SECTION
The AD7937 contains two identical 12-bit multiplying D/A
converters. Each DAC consists of a highly stable R-2R ladder
and 12 N-channel current steering switches. Figure 2 shows a
simplified D/A circuit for DAC A. In the R-2R ladder, binary
weighted currents are steered between IOUTA and AGNDA. The
current flowing in each ladder leg is constant, irrespective of
switch state. The feedback resistor RFBA is used with an op amp
(see Figures 4 and 5) to convert the current flowing in IOUTA to
a voltage output.
VREFA
R
2R
S11
R
2R
2R 2R
S10
S0
RFBA
R
IOUTA
AGNDA
Figure 2. Simplified Circuit Diagram for DAC A
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for one of the D/A con-
verters (DAC A) in the AD7937. A similar equivalent circuit
can be drawn for DAC B.
R
RFBA
VREFA
IOUTA
R
D.VREF
R
RO
ILKG
COUT
AGNDA
Figure 3. Equivalent Analog Circuit for DAC A
COUT is the output capacitance due to the N-channel switches
and varies from about 50 pF to 100 pF with digital input code.
The current source ILKG is composed of surface and junction
leakages and approximately doubles every 10°C. RO is the equiva-
lent output resistance of the device which varies with input code.
DIGITAL CIRCUIT INFORMATION
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA.
Table I. AD7937 Truth Table
CLR UPD CS WR A1 A0 Function
1 1 1 X X X No Data Transfer
1 1 X 1 X X No Data Transfer
0 X X X X X All Registers Cleared
1 1 0 0 0 0 DAC A LS Input Register
Loaded with DB7–DB0 (LSB)
1 1 0 0 0 1 DAC A MS Input Register
Loaded with DB3 (MSB)–DB0
1 1 0 0 1 0 DAC B LS Input Register
Loaded with DB7–DB0 (LSB)
1 1 0 0 1 1 DAC B MS Input Register
Loaded with DB3 (MSB)–DB0
1 0 1 0 X X DAC A, DAC B Registers
Updated Simultaneously from
Input Registers
1 0 0 0 X X DAC A, DAC B Registers are
Transparent
NOTE: X = Don’t care
–4–
REV. 0
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